The present invention relates to modifying alignment marks formed on surfaces of planar and near-planar integrated circuit (IC) substrates. The present invention more particularly relates to introducing a step in alignments marks formed on integrated circuit (IC) substrates using equipment related to chemical mechanical polishing.
FIG. 1 shows a top view of a portion of an IC substrate surface 10. A scribe line region 14, which is defined by scribe lines 6 and 8, is shown flanked by two active die regions 12 on IC substrate surface 10. After the fabrication of the IC substrate concludes, IC substrate surface 10 is cut along scribe lines 6 and 8 to form individual ICs or chips. Typically in scribe line region 14, a plurality of alignment marks or targets 16 are fabricated to facilitate the alignment of one layer to another subsequently deposited layer as described below. Furthermore, alignment marks 16 typically remain on the IC substrate surface during the various steps of IC substrate fabrication, e.g., deposition of various layers, photolithography, etching, etc. and after the fabrication of IC substrate has concluded, they may be discarded when IC substrate surface 10 is cut along scribe lines 6 and 8.
FIGS. 2A-2C show some major steps involved in the fabrication of one of alignment marks 16 on a surface of an IC substrate 20. The fabrication of alignment mark 16 may begin when a trench 24 is etched in a dielectric layer 22, as shown in FIG. 2A. According to FIG. 2B, a layer of metal 26 is then deposited on the surface of IC substrate 20, filling trench 24. Next, the surface of IC substrate 20 is subjected to chemical-mechanical polishing for polishing layer of metal 26 disposed above dielectric layer 22 and form alignment mark 16 as shown in FIG. 2C. Chemical-mechanical polishing (sometimes referred to as "CMP") typically involves mounting IC substrates face down on a substrate holder and rotating the IC substrate against a polishing pad mounted on a platen, which is in turn rotating or is in orbital state. A slurry containing a chemical that chemically interacts with the facing IC substrate layer and an abrasive that physically removes that layer is flowed between the IC substrate and the polishing pad or on the pad near the IC substrate. In semiconductor wafer fabrication, this technique is used to planarize various wafer layers such as dielectric layers, metallization layers etc.
An interconnect layer, e.g., a metal layer, is typically then blanket deposited on surface of IC substrate 20. Before the interconnect layer is patterned to form the various interconnects, however, an alignment tool aligns the placement of a reticle such that the circuit pattern to form the various interconnects is transferred to appropriate locations on the IC substrate surface. In other words, in order to ensure the formation of electrically conductive pathways in the IC substrate, the patterned interconnect layer should align to an underlying conductive layer that forms plugs, e.g., via plugs and contact plugs, which are the vertical interconnects between two successively deposited interconnect layers or between an interconnect layer and transistor device elements disposed below the interconnect layer, respectively.
Unfortunately, alignment marks, fabricated as described above, fail to effectively align a conductive layer (underlying a metal layer) to the metal layer. The alignment tool attempts to align the underlying conductive plug layer to the metal layer disposed above by detecting an optical difference, e.g., contrast due to topography, on the metal layer because the metal layer is opaque and not transparent like the dielectric layer. The alignment tool, however, fails to detect a contrast on the metal layer because the substantially planar IC substrate surface underlying the metal layer is devoid of any topography, e.g., hills or valleys, that generates the necessary contrast during alignment. Those skilled in the art will recognize that the effect of a misaligned mask layer can cause the entire circuit in an IC substrate to fail.
What is therefore needed is a process of making a modified alignment mark, which effectively facilitates an alignment tool to align an underlying layer to a an opaque layer, e.g., metal layer, that is disposed above.